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ds05-11305-2e fujitsu semiconductor data sheet memory cmos 1 m 16 bits hyper page mode dynamic ram MB8116165B-50/-60 cmos 1,048,576 16 bits hyper page mode dynamic ram n description the fujitsu mb8116165b is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 16-bit increments. the mb8116165b features a ?yper page mode of operation whereby high-speed random access of up to 256-bits of data within the same row can be selected. the mb8116165b dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb8116165b is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb8116165b is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb8116165b are not critical and all inputs are ttl compatible. n product line & features parameter MB8116165B-50 mb8116165b-60 ras access time 50 ns max. 60 ns max. random cycle time 84 ns min. 104 ns min. address access time 25 ns max. 30 ns max. cas access time 15 ns max. 15 ns max. hyper page mode cycle time 20 ns min. 25 ns min. low power dissipation operating current 660 mw max. 550 mw max. standby current 11 mw max. (ttl level) / 5.5 mw max. (cmos level) 1,048,576 words 16 bits organization silicon gate, cmos, advanced stacked capacitor cell all input and output are ttl compatible 4,096 refresh cycles every 65.6 ms early write or oe controlled write capability ras -only, cas -before-ras , or hidden refresh hyper page mode, read-modify-write capability on chip substrate bias generator for high performance this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
2 MB8116165B-50/-60 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7.0 v voltage of v cc supply relative to v ss v cc ?.5 to +7.0 v power dissipation p d 1.0 w short circuit output current i out ?0 to +50 ma operating temperature t ope 0 to +70 c storage temperature t stg ?5 to +125 c package and ordering information ?42-pin plastic (400 mil) soj, order as mb8116165b- pj ?50-pin plastic (400 mil) tsop (ii) with normal bend leads, order as mb8116165b- pftn plastic soj package plastic tsop (ii) package (lcc-42p-m01) (fpt-50p-m06) (normal bend)
3 MB8116165B-50/-60 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol max. unit input capacitance, a 0 to a 11 c in1 5pf input capacitance, ras , lcas , ucas , we , oe c in2 5pf input/output capacitance, dq 1 to dq 16 c dq 7pf fig. 1 mb8116165b dynamic ram - block diagram mode control write clock gen a 2 a 1 a 4 a 3 a 6 a 5 a 8 a 7 a 9 a 0 ras lcas ucas clock gen #2 data in buffer we dq 1 to dq 16 oe v cc v ss data out buffer column decoder clock gen #1 sense amp & i/o gate 16,777,216 bit storage cell address buffer & pre- decoder refresh address counter row decoder substrate bias gen a 10 a 11
4 MB8116165B-50/-60 n pin assignments and descriptions address inputs row : a 0 to a 11 column : a 0 to a 7 refresh : a 0 to a 11 1 pin index v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 dq 1 dq 2 dq 3 dq 4 v cc v ss v ss dq 5 dq 6 dq 7 dq 8 dq 16 dq 15 dq 14 dq 13 v ss 21 22 n.c. n.c. a 11 a 10 a 0 a 1 a 2 a 3 v cc dq 12 dq 11 dq 10 dq 9 n.c. a 9 a 8 a 7 a 6 a 5 a 4 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 21 30 v cc dq 1 dq 2 dq 3 dq 4 v cc v ss dq 5 dq 6 dq 7 dq 8 dq 16 dq 15 dq 14 dq 13 v ss n.c. dq 12 dq 11 dq 10 dq 9 n.c. 22 29 23 28 24 27 25 26 n.c. a 0 a 1 a 2 a 3 v cc n.c. v ss n.c. a 9 a 8 a 7 a 6 a 5 a 4 1 pin index 42-pin soj (top view) 50-pin tsop (ii) (top view) we ras lcas ucas oe we ras lcas ucas oe a 11 a 10 designator function a 0 to a 11 ras row address strobe lcas lower column address strobe ucas upper column address strobe we write enable oe output enable dq 1 to dq 16 data input/output v cc +5.0 volt power supply v ss circuit ground n.c. no connection
5 MB8116165B-50/-60 n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs twenty input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. since only twelve address bits (a 0 to a 11 ) are available, the column and row inputs are separately strobed by lcas or ucas and ras as shown in figure 1. first, twelve row address bits are input on pins a 0 -through-a 11 and latched with the row address strobe (ras ) then, eight column address bits are input and latched with the column address strobe (lcas or ucas ). both row and column addresses must be stable on or before the falling edges of ras and lcas or ucas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways: an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or lcas /ucas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data of dq 1 to dq 8 is strobed by lcas and dq 9 to dq 16 is strobed by ucas and the setup/hold times are referenced to each lcas and ucas because we goes low before lcas /ucas . in a delayed write or a read-modify-write cycle, we goes low after lcas /ucas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs and high-z state are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of lcas (for dq 1 to dq 8 ) ucas (for dq 9 to dq 16 ) when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max), and t rcd (max) is satis?d. t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . t oez : from oe inactive. t off : from cas inactive while ras inactive. t ofr : from ras inactive while cas inactive. t wez : from we active while cas inactive. the data remains valid after either oe is inactive, or both ras and lcas (and/or ucas ) are inactive, or cas is reactived. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage *1 v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 000 input high voltage, all inputs *1 v ih 2.4 6.5 v input low voltage, all inputs* *1 v il ?.3 0.8 v
6 MB8116165B-50/-60 hyper page mode operation the hyper page mode operation provides faster memory access and lower power dissipation. the hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each page of memory (within column address locations), any of 256 16-bits can be accessed and, when multiple mb8116165bs are used, cas is decoded to select the desired memory page. hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. hyper page mode features that output remains valid when cas is inactive until cas is reactivated.
7 MB8116165B-50/-60 n dc characteristics (at recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol condition value unit min. typ. max. output high voltage *1 v oh i oh = ?.0 ma 2.4 v output low voltage *1 v ol i ol = +4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in v cc ; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i do(l) 0 v v out v cc ; data out disabled ?0 10 operating current (average power supply current) *2 MB8116165B-50 i cc1 ras & lcas , ucas cycling; t rc = min 120 ma mb8116165b-60 100 standby current (power supply current) ttl level i cc2 ras = lcas = ucas = v ih 2.0 ma cmos level ras = lcas = ucas 3 v cc ?.2 v 1.0 refresh current #1 (average power supply current) *2 MB8116165B-50 i cc3 lcas = ucas = v ih , ras cycling; t rc = min 120 ma mb8116165b-60 100 hyper page mode current *2 MB8116165B-50 i cc4 ras = v il , lcas = ucas cycling; t hpc = min 120 ma mb8116165b-60 100 refresh current #2 (average power supply current) *2 MB8116165B-50 i cc5 ras cycling; cas -before-ras ; t rc = min 120 ma mb8116165b-60 100
8 MB8116165B-50/-60 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol MB8116165B-50 mb8116165b-60 unit min. max. min. max. 1 time between refresh t ref 65.6 65.6 ms 2 random read/write cycle time t rc 84 104 ns 3 read-modify-write cycle time t rwc 114 138 ns 4 access time from ras *6,9 t rac ?0?0ns 5 access time from cas *7,9 t cac ?5?5ns 6 column address access time *8,9 t aa ?5?0ns 7 output hold time t oh 3?ns 8 output hold time from cas t ohc 5?ns 9 output buffer turn on delay time t on 0?ns 10 output buffer turn off delay time *10 t off ?3?5ns 11 output buffer turn off delay time from ras *10 t ofr ?3?5ns 12 output buffer turn off delay time from we *10 t wez ?3?5ns 13 transition time t t 150150ns 14 ras precharge time t rp 30?0ns 15 ras pulse width t ras 50 100000 60 100000 ns 16 ras hold time t rsh 13?5ns 17 cas to ras precharge time *21 t crp 5?ns 18 ras to cas delay time *11,12,22 t rcd 11 35 14 45 ns 19 cas pulse width t cas 7 10 ns 20 cas hold time t csh 38?0ns 21 cas precharge time (normal) *19 t cpn 7 10 ns 22 row address set up time t asr 0?ns 23 row address hold time t rah 7 10 ns 24 column address set up time t asc 0?ns 25 column address hold time t cah 7 10 ns 26 column address hold time from ras t ar 18?4ns 27 ras to column address delay time *13 t rad 9 251230ns 28 column address to ras lead time t ral 25?0ns 29 column address to cas lead time t cal 18?3ns 30 read command set up time t rcs 0?ns 31 read command hold time referenced to ras *14 t rrh 0?ns
9 MB8116165B-50/-60 (continued) no. parameter notes symbol MB8116165B-50 mb8116165b-60 unit min. max. min. max. 32 read command hold time referenced to cas *14 t rch 0?ns 33 write command set up time *15,20 t wcs 0?ns 34 write command hold time t wch 7 10 ns 35 write hold time from ras t wcr 18?4ns 36 we pulse width t wp 7 10 ns 37 write command to ras lead time t rwl 13?5ns 38 write command to cas lead time t cwl 7 10 ns 39 din set up time t ds 0?ns 40 din hold time t dh 7 10 ns 41 data hold time from ras t dhr 18?4ns 42 ras to we delay time *20 t rwd 65?7ns 43 cas to we delay time *20 t cwd 30?2ns 44 column address to we delay time *20 t awd 40?7ns 45 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 46 cas set up time for cas -before- ras refresh t csr 0?ns 47 cas hold time for cas -before-ras refresh t chr 10?0ns 48 access time from oe *9 t oea ?5?5ns 49 output buffer turn off delay from oe *10 t oez ?3?5ns 50 oe to ras lead time for valid data t oel 5?ns 51 oe to cas lead time t col 5?ns 52 oe hold time referenced to we *16 t oeh 5?ns 53 oe to data in delay time t oed 13?5ns 54 ras to data in delay time t rdd 13?5ns 55 cas to data in delay time t cdd 13?5ns 56 din to cas delay time *17 t dzc 0?ns 57 din to oe delay time *17 t dzo 0?ns 58 oe precharge time t oep 5?ns 59 oe hold time referenced to cas t oech 7 10 ns 60 we precharge time t wpz 5?ns 61 we to data in delay time t wed 13?5ns 62 hyper page mode ras pulse width t rasp 100000 100000 ns
10 MB8116165B-50/-60 (continued) no. parameter notes symbol MB8116165B-50 mb8116165b-60 unit min. max. min. max. 63 hyper page mode read/write cycle time t hpc 20?5ns 64 hyper page mode read-modify- write cycle time t hprwc 59?9ns 65 access time from cas precharge *9,18 t cpa ?0?5ns 66 hyper page mode cas precharge time t cp 7 10 ns 67 hyper page mode ras hold time from cas precharge t rhcp 30?5ns 68 hyper page mode cas precharge to we delay time *20 t cpwd 45?2ns
11 MB8116165B-50/-60 notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rates; the specified values are obtained with the output open. i cc depends on the number of address change as ras = v il , ucas = v ih , lcas = v ih and v il > ?.3 v. i cc1 , i cc3 , i cc4 and i cc5 are specified at one time of address change during ras = v il and ucas = v ih , lcas = v ih . i cc2 is specified during ras = v ih and v il > ?.3 v. *3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 2 ns. *5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min) and v il (max). *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig.2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *9. measured with a load equivalent to two ttl loads and 100 pf. *10. t off , t ofr , t wez and t oez are speci?d that output buffer change to high-impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min) + 2t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satisfied for a read cycle. *15. t wcs is specified as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satisfied. *18. t cpa is access time from the selection of a new column address (that is caused by changing both ucas and lcas from ??to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). *19. assumes that cas -before-ras refresh. *20. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min), the cycle is an early write cycle and d out pin will maintain high-impedance state throughout the entire cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , and t ral specifications. *21. the last cas rising edge. *22. the first cas falling edge.
12 MB8116165B-50/-60 n functional truth table x : ? or ? * : it is impossible in hyper page mode. operation mode clock input address input input/output data refresh note ras lcas ucas we oe row column dq 1 to dq 8 dq 9 to dq 16 input output input output standby h h h x x high-z high-z read cycle l l h l h l l hl valid valid valid high-z valid high-z valid valid yes* t rcs 3 t rcs (min) write cycle (early write) l l h l h l l lx valid valid valid valid high-z valid valid high-z yes* t wcs 3 t wcs (min) read-modify- write cycle l l h l h l l h ? ll ? h valid valid valid valid valid high-z valid valid valid high-z valid valid yes* ras -only refresh cycle lhhxx valid high-z high-z yes cas -before- ras refresh cycle lllxx high-z high-z yes t csr 3 t csr (min) hidden refresh cycle h ? l l h l h l l h ? xl valid high-z valid high-z valid valid yes previous data is kept. fig. 2 ?t rac vs. t rcd fig. 4 ?t cpa vs. t cp fig. 3 ?t rac vs. t rad t rcd (ns) t rad (ns) t cp (ns) t rac (ns) t rac (ns) t cpa (ns) 60 40 100 80 120 20 060 40 100 80 60 50 80 70 90 20 040 30 60 50 50 ns version 40 30 60 50 70 10 030 20 50 40 60 ns version 60 ns version 50 ns version 10 50 ns version 60 ns version
13 MB8116165B-50/-60 t rc t ras t ar t rp t cdd t rcd t crp t asr t rah t asc t cah t oel t rch t rcs t dzc t oea t dzo t on t oed t oh t off row add column add t ral t cal t aa t cac t rac high-z high-z t oh t csh t rsh t cas t on t wpz t wez t oez t rad t col a 0 to a 11 lcas or ucas v ih v il v ih v il we v oh v ol ras v ih v il v ih v il dq (output) v ih v il dq (input) v ih v il oe description to implement a read operation, a valid address is latched by the ras and lcas or ucas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. dq pins are valid when ras and cas are high or until oe goes high. the access time is determined by ras (t rac ), lcas /ucas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either lcas /ucas or oe goes high, the output returns to a high-impedance state after t oh is satisfied. fig. 5 ?read cycle valid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t rdd t rrh t wed
14 MB8116165B-50/-60 t rc t ras t rp t csh t rcd t crp t cas t asr t rah t asc t cah high-z row add column add t wcr t wcs t wch t dh t ds valid data in t rsh t ar t dhr lcas or ucas v ih v il a 0 to a 11 v ih v il v ih v il we v oh v ol ras v ih v il dq (output) v ih v il dq (input) description a write cycle is similar to a read cycle except we is set to a low state and oe is an ??or ??signal. a write cycle can be implemented in either of three ways ?early write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satisfied. in the early write cycle shown above t wcs satisfied, data on the dq pins are latched with the falling edge of lcas or ucas and written into memory. fig. 6 ?early write cycle ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
15 MB8116165B-50/-60 t rc t ras t cas t rcd t asr t cah t rcs t dzc t csh t rp t asc t rah t cwl t wp t ds t dh t oed t dzo t oeh row add col add t rsh t wch t rwl high-z high-z high-z t on t on t ar t oez lcas or ucas v ih v il a 0 to a 11 v ih v il v ih v il we v oh v ol ras v ih v il dq (output) v ih v il dq (input) description in the delayed write cycle, t wcs is not satisfied; thus, the data on the dq pins are latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 7 ?delayed write cycle (oe controlled) v ih v il oe invalid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t crp valid data i n
16 MB8116165B-50/-60 t rwc t ras t rcd t asr t cah t rwl t rcs t rp t asc t rah t cwl t ds t dh t oed t dzo t oeh t rad t cwd t wp valid data t oez t oh t rwd t awd t dzc high-z t cac t rac t aa high-z high-z valid data i n t ar t on t oea t on t crp lcas or ucas v ih v il description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. fig. 8 ?read-modify-write cycle ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il v ih v il we v oh v ol ras v ih v il dq (output) v ih v il dq (input) v ih v il oe row add col add
17 MB8116165B-50/-60 t rasp t asc t rcs t rhcp t rp t rcd t cas t rsh t hpc t cas t cas t cp t rch t rcs t rch t rcs t dzc t cah t cah t rah t asc t rrh t cah t asc t rch t on t cac t on t rad t csh t ral t dzo t aa high-z t rac t rdd t oh t ofr t off t oh t oh t on t ohc t cac t ohc during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t off t oed t oez lcas or ucas v ih v il description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. fig. 9 ?hyper page mode read cycle valid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) ras v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il a 0 to a 11 v ih v il t crp t asr t ar row add col add col add col add high-z t aa t cdd t cpa t cpa
18 MB8116165B-50/-60 t rasp t asc t rcs t rhcp t rp t rcd t cas t rsh t hpc t cas t dzc t cah t cah t rah t asc t rrh t cah t asc t rch t cac t rad t ral high-z t ofr high-z t off t oh t oez t oed during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t rdd t oh t aa t cac t aa t on t oea t oep t oh t oech t oez t oh t oez t oea t dzo t on t rac t cp t cdd t col t oea t cac t cpa t ohc t ar t cal t csh t cp t crp t asr lcas or ucas v ih v il description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. fig. 10 ?hyper page mode read cycle (oe = ??or ?? valid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il ras v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il t cas row add col add col add col add t aa t cpa t oh high-z
19 MB8116165B-50/-60 t rasp t asc t rhcp t rp t cas t rsh t hpc t cas t cas t dzc t csh t cah t rah t asc t csh t asc t rch t cac t aa t csh t ral high-z high-z t off t oh t oez t oed during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t oh t oh t aa t cac t aa t oea t dzo t on t rac t rcd t ofr t rcs t rch t rcs t rch t cal t wez t cac t on high-z t on t wez t wpz t wez t on t rad t rcs t rdd t cdd t crp t asr description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. fig. 11 ?hyper page mode read cycle (we = ??or ?? valid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il ras v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il lcas or ucas v ih v il row add col add col add col add t wed t wpz t wpz
20 MB8116165B-50/-60 t rasp t rp row add t rsh t hpc t rcd t csh t cas t asc t cah col add col add high-z t cas t cp col add t cah t asc t cah valid data valid data valid data t wcs t wch t wcs t wch t wcs t wch t ds t dh t asc t ds t dh t ds t dh t ar t wcr t dhr t rhcp during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t cwl t rwl t cwl t cas t crp t rah t asr lcas or ucas v ih v il description the hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of we and oe are reversed. data appearing on the dq 1 to dq 8 is latched on the falling edge of lcas and one appearing on the dq 9 to dq 16 is latched on the falling edge of ucas and the data is written into the memory. during the hyper page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satisfied. fig. 12 ?hyper page mode early write cycle ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il ras v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il t cwl t ral
21 MB8116165B-50/-60 valid valid col add col add row add high-z data i n data i n lcas or ucas description the hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the hyper page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 13 ?hyper page mode delayed write cycle invalid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il ras v ih v il v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il t rp t cp t rasp t hpc t csh t rcd t rah t ar t asc t cah t cah t asc t cwl t crp t asr t cas t rsh t cas t rcs t wch t wp t cwl t wch t wp t rwl t ds t dh t dh t ds t dzc t oeh t oed t on t on t on t oed t oeh t oez t oez t on t dzo
22 MB8116165B-50/-60 valid col add col add row add col add high-z data i n high-z high-z lcas or ucas v ih v il description the hyper page mode performs read/write operations repetitively during one ras cycle. at this time, t hpc (min) is invalid. fig. 14 ?hyper page mode read/write mixed cycle valid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il ras v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il t rasp t cp t csh t rcd t crp t cas t cas t hpc t cas t rsh t rp t asr t rah t rad t asc t cah t asc t ral t cah t cah t rhcp t cal t asc t rcs t rch t wcs t wch t wed t ds t dh t dzc t aa t cac t ohc t aa t cac t wez t oez t oed t on t dzo t on t oea t rac t cpa
23 MB8116165B-50/-60 valid valid col add row add col add high-z lcas or ucas v ih v il description during the hyper page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. fig. 15 ?hyper page mode read-modify-write cycle valid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il ras v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il data data t rasp t cp t crp t rcd t cwd t rwl t hprwc t cwd t asc t cah t cah t asc t rad t rah t asr t rp t rcs t cwl t wp t rcs t wp t cwl t rwd t dzc t ds t ds t dh t dh t cpwd t awd t oed t cac t on t on t rac t dzo t oez t oea t cpa t oea t on t oeh t oez t oeh t cac t on t aa t oed t aa
24 MB8116165B-50/-60 t rc high-z t ras t rpc t cpn t csr t chr t rp t off t oh t csr t cpn t rc t rp t asr t rpc high-z t rah t oh t crp t ras t off row address t crp lcas or ucas lcas or ucas a 0 to a 11 v ih v il v oh v ol ras v ih v il v ih v il dq (output) fig. 16 ?ras -only refresh (we = oe = ??or ?? description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 4,096 row addresses every 65.6-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and lcas and ucas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. v oh v ol ras v ih v il v ih v il dq (output) fig. 17 ?cas -before-ras refresh (addresses = we = oe = ??or ?? description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if lcas or ucas is held low for the specified setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas -before-ras refresh operation. ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
25 MB8116165B-50/-60 t rc t rp t chr t rc t ras t ras t rp t oel t rsh t rah t asc t cah t rcs t rrh t cac t dzc t cdd t dzo t oea t oed t oez t crp t asr t off t on valid data out t rcd t ral t ar t aa t rac high-z high-z t ofr t oh t rad t oh lcas or ucas description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. fig. 18 ?hidden refresh cycle ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) a 0 to a 11 v ih v il ras v ih v il v ih v il we v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il row address column address
26 MB8116165B-50/-60 t csr t rp t rcs t fcah t asc t cwl t wp t chr t frsh t rwl t fcwd t dh t ds t dzc t oed t on t dzo t oez t oeh valid data in column addresses t fcac high-z high-z t fcas t oea t cp lcas , ucas a 0 to a 11 ras dq (output) fig. 19 ?cas -before-ras refresh counter test cycle we oe dq (input) description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the function of cas -before-ras refresh circuitry. if a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are defined as follows: row addresses: bits a 0 through a 11 are de?ed by the on-chip refresh counter. column addresses: bits a 0 through a 7 are de?ed by latching levels on a 0 to a 7 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows; 1) initialize the internal refresh address counter by using 8 ras -only refresh cycles. 2) use the same column address throughout the test. 3) write ??to all 4,096 row addresses at the same column address by using normal write cycles. 4) read ??written in procedure 3) and check; simultaneously write ??to the same addresses by using cas - before-ras refresh counter test (read-modify-write cycles). repeat this procedure 4,096 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 4,096 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). mb8116165b-60 MB8116165B-50 unit parameter min . max. ns no . min. max. 69 50 45 symbol (at recommended operating conditions unless otherwise noted.) cas to we delay time 70 35 ns 35 column address hold time cas pulse width 70 ns 63 50 ns 45 ns 45 50 access time from cas t fcac t fcah t fcwd t fcas t frsh ras hold time 71 72 73 note: assumes that cas -before-ras refresh counter test cycle only. valid data ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) high-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il
27 MB8116165B-50/-60 n package dimensions 42-lead plastic leaded chip carrier (case no.: lcc-42p-m01) +0.35 C0.20 +.014 C.008 C.001 +.002 C0.02 +0.05 * lead no 3.40 .134 .008 0.20 (.370.020) 9.400.51 r0.81(.032)typ 0.64(.025)min 2.75(.108)nom details of "a" part 0.81(.032)max. 0.430.10(.017.004) 42 22 21 1 0.10(.004) 2.50(.098)nom (.432.005) 10.970.13 (.400) nom 10.16 index (.050.005) 1.270.13 25.40(1.000)ref 27.300.13(1.075.005) "a" ? 1994 fujitsu limited c42001s-2c-1 * this dimension exclude resin protrusion.(each side : .015(.006)max) dimensions in mm (inches)
28 MB8116165B-50/-60 n package dimensions 1.150.05(.045.002) (.010) (.006) 0.25 0.15 (.005.002) 0.1250.05 * "a" 0.40(.016)max 0.15(.006)max details of "a" part 0.500.10 (.020.004) 10.760.20 (.424.008) 11.760.20 (.463.008) 10.160.10 (.400.004) 19.20(.756)ref 0.10(.004) 0.80(.031)typ 0.05(.002)min (stand off) 0.13(.005) m 0.300.10 (.012.004) 20.950.10(.825.004) lead no. index 25 15 11 1 26 36 40 50 1994 fujitsu limited f50006s-2c-1 c 50-lead plastic flat package (case no.: fpt-50p-m06) dimensions in mm (inches) * this dimension exclude resin protrusion.(each side : .015(.006)max)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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